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ICX274AL
Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for B/W Video Cameras
Description The ICX274AL is a diagonal 8.923mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 2.01M effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/15 second, and output is also possible using various addition and pulse elimination methods. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still images without a mechanical shutter. Further, high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for image input applications such as still cameras which require high resolution, etc. Features * High horizontal and vertical resolution * Supports the following modes Progressive scan mode (with/without mechanical shutter) 2/8-line readout mode 2/4-line readout mode 2-line addition mode Center scan modes (1), (2) and (3) AF modes (1) and (2) * Square pixel * Horizontal drive frequency: 28.6364MHz (typ.), 36.0MHz (max.) * Reset gate bias are not adjusted * High sensitivity, low dark current * Continuous variable-speed shutter function * Excellent anti-blooming characteristics * 20-pin high-precision plastic package 20 pin DIP (Plastic)
Pin 1 2
V
10 12 Pin 11 H 48
Optical black position (Top View)
Device Structure * Interline CCD image sensor * Image size: Diagonal 8.923mm (Type 1/1.8) * Total number of pixels: 1688 (H) x 1248 (V) approx. 2.11M pixels * Number of effective pixels: 1628 (H) x 1236 (V) approx. 2.01M pixels * Number of active pixels: 1620 (H) x 1220 (V) approx. 1.98M pixels * Recommended number of recording pixels: 1600 (H) x 1200 (V) approx. 1.92M pixels * Chip size: 8.50mm (H) x 6.80mm (V) * Unit cell size: 4.40m (H) x 4.40m (V) * Optical black: Horizontal (H) direction: Front 12 pixels, rear 48 pixels Vertical (V) direction: Front 10 pixels, rear 2 pixels * Number of dummy bits: Horizontal 28 Vertical 1 * Substrate material: Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E01X50C34
ICX274AL
Block Diagram and Pin Configuration (Top View)
VOUT GND V2C V3C V2B V2A V3B V3A V1 V4
10
9
8
7
6
5
4
3
2
1
Vertical register
Note) Horizontal register Note) : Photo sensor
11
VDD
12
RG
13
H2B
14
H1B
15
GND
16
SUB
17
CSUB
18
VL
19
H1A
20
H2A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol V4 V3A V3B V3C V2A V2B V2C V1 GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Signal output Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol VDD RG H2B H1B GND SUB CSUB VL H1A H2A Description Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock GND Substrate clock Substrate bias1 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock
1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1F.
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ICX274AL
Absolute Maximum Ratings Item VDD, VOUT, RG - SUB V2, V3 - SUB ( = A to C) Against SUB V1, V4, VL - SUB H1, H2, GND - SUB ( = A, B) CSUB - SUB VDD, VOUT, RG, CSUB - GND Against GND V1, V2, V3, V4 - GND ( = A to C) H1, H2 - GND ( = A, B) Against VL V2, V3 - VL ( = A to C) V1, V4, H1, H2, GND - VL ( = A, B) Voltage difference between vertical clock input pins Between input clock pins H1 - H2 ( = A, B) H1, H2 - V4 ( = A, B) Storage temperature Guaranteed temperature of performance Operating temperature Ratings -40 to +12 -50 to +15 -50 to +0.3 -40 to +0.3 -25 to -0.3 to +22 -10 to +18 -10 to +6.5 -0.3 to +28 -0.3 to +15 to +15 -6.5 to +6.5 -10 to +16 -30 to +80 -10 to +60 -10 to +75 Unit V V V V V V V V V V V V V C C C 2 Remarks
2 +24V (Max.) is guaranteed when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed during power-on or power-off.
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ICX274AL
Bias Conditions Item Supply voltage Protective transistor bias Substrate voltage adjustment range No line addition1 2-line addition2 Symbol VDD VL VSUB VSUB2 VSUB RG 8.8 Indicated voltage - 0.2 Indicated voltage 5 Min. 14.55 Typ. 15.0 3 Max. 15.45 Unit Remarks V
Internally generated value 14.4 Indicated voltage + 0.2 V V V
4
Substrate voltage adjustment accuracy Reset gate clock
1 Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3), and AF modes (1) and (2) 2 2-line addition mode and center scan mode (2) 3 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. 4 Substrate voltage (VSUB2) setting value indication The substrate voltage (VSUB) for modes without line addition is generated internally. The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage. VSUB2 code - 1-digit indication VSUB2 code The code and the actual value correspond as follows. VSUB2 code Actual value VSUB2 code 1 8.8 J 2 9.0 K 3 9.2 L 4 9.4 m 6 9.6 N 7 9.8 P 8 9 A C d E f G h
10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 R S U V W X Y Z
Actual value 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4 [Example] "h" indicates a VSUB2 setting of 11.6V. 5 Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD. DC characteristics Item Supply current Symbol IDD Min. 7.0 Typ. 10.0 Max. 13.0 Unit mA Remarks
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ICX274AL
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL VH Horizontal transfer clock voltage VHL VCR VRG Reset gate clock voltage Substrate clock voltage VRGLH - VRGLL VRGL - VRGLm VSUB 21.5 22.5 4.75 -0.05 0.8 3.0 5.0 0 2.5 3.3 5.25 0.4 0.5 23.5 Min. 14.55 -0.05 -0.2 -8.0 6.8 -0.25 -0.25 Typ. 15.0 0 0 -7.5 7.5 Max. 15.45 0.05 0.05 -7.0 8.05 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 Unit V V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 Low-level coupling Low-level coupling Cross-point voltage High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks
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ICX274AL
Clock Equivalent Circuit Constants Item CV1 CV2A, CV2B Capacitance between vertical transfer clock and GND CV2C CV3A, CV3B CV3C CV4 CV12 (A, B) CV12C CV13 (A, B) CV13C CV14 CV2 (A, B), 3 (A, B) Capacitance between vertical transfer clocks CV2 (A, B), 3C CV2 (A, B), 4 CV2C, 3 (A, B) CV2C, 3C CV2C, 4 CV3 (A, B), 4 CV3C, 4 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Horizontal transfer clock ground resistor Reset gate clock and series resistor CH1 CH2 CHH CRG CSUB R1, R4 R2 (A, B, C), 3 (A, B, C) RGND RH RH2 RRG Symbol Min. Typ. 3300 1200 2700 1000 1800 6800 120 220 150 270 2700 470 680 680 1000 820 1800 820 1500 100 100 47 2 820 30 62 15 7 20 4.7 Max. Unit Remarks pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF k
Note 1) Expressions using parentheses such as CV2 (A,B), 3C indicate items which include all combinations of the pins within the parentheses. For example, CV2 (A, B), 3C indicates [CV2A3C, CV2B3C].
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ICX274AL
V1
RH H1A
R1 CV1
RH H2A
RH H1B CHH
RH H2B
CV14 CV24 ( = A to C)
CV12 ( = A to C)
CH1
V4 R4 CV4 CV34 ( = A to C) CV13 ( = A to C) RGND V2 ( = A to C) R2 ( = A to C) CV2 ( = A to C) CV23 ( = A to C) CV3 ( = A to C) R3 ( = A to C)
RRG
CH2
RH2
Horizontal transfer clock equivalent circuit
V3 ( = A to C)
RG
Note 2) C22 and C33 ( = A to C, = A to C other than ) are sufficiently small relative to other capacitance between other vertical clocks in the equivalent circuit, so these are omitted from the equivalent circuit diagram. Vertical transfer clock equivalent circuit
CRG
Reset gate clock equivalent circuit
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ICX274AL
Drive Clock Waveform Conditions (1) Readout clock waveform
100% 90%
M VVT 10% 0% tr twh tf 0V M 2
(2) Vertical transfer clock waveform
V1
VVH1
V3A, V3B, V3C
VVHH
VVHH
VVH VVHL
VVHH VVHL VVHL
VVHH VVHL
VVH
VVH3
VVL1
VVLH
VVL3
VVLH VVLL VVL
VVLL VVL
V2A, V2B, V2C
VVHH VVHH VVH VVHL VVH2 VVHL
V4
VVH VVHH VVHH
VVHL VVH4
VVHL
VVL2VVLH VVLL VVL4
VVLH
VVLL VVL
VVL
VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4)
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ICX274AL
(3) Horizontal transfer clock waveform
tr H2 90% VCR VH VH 2 10% H1 two VHL twh tf
twl
Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. ( = A, B) (4) Reset gate clock waveform
tr twh tf
RG waveform
VRGH
twl VRG Point A VRGLH VRGLL VRGLm VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform
100% 90%
M VSUB 10% VSUB 0% (Internally generated bias) M 2 tf
tr
twh
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ICX274AL
Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz) Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V4, V2, V3 ( = A to C) H1 ( = A, B) 10 12.5 H2 ( = A, B) 10 12.5 4 7 2.1 10 12.5 10 12.5 24 5 5 2 0.5 7.5 7.5 twh twl tr tf Unit s 400 ns 5 5 3 7.5 7.5 Remarks During readout 1 2
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 3.3 3.5 0.5 15 0.5
ns ns
Reset gate clock RG Substrate clock SUB
0.5 s
When draining charge
Item Horizontal transfer clock
Symbol H1A, H1B, H2A, H2B
two Min. Typ. Max. 8 10
Unit ns
Remarks
Clock Switching Characteristics (Horizontal drive frequency: 36MHz) Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V4, V2, V3 ( = A to C) H1 ( = A, B) 8 H2 ( = A, B) 8 4 9 9 5.5 1.67 8 8 9 9 8 5 5 2 0.25 6 6 twh twl tr tf Unit s 400 ns 5 5 3 6 6 Remarks During readout 1 2
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 4.0 4.2 0.5 15 0.5
ns ns
Reset gate clock RG Substrate clock SUB
0.25 s
When draining charge
Item Horizontal transfer clock
Symbol H1A, H1B, H2A, H2B
two Min. Typ. Max. 8 9
Unit ns
Remarks
1 When two vertical transfer clock drivers CXD3400N are used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 ( = A, B) rising side of the H1 and H2 waveforms must be VH/2 [V] or more. - 10 -
ICX274AL
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0 0.9 0.8 0.7
Relative Response
0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wave Length [nm] 800 900 1000
Image Sensor Characteristics Item Sensitivity Saturation signal Symbol S Vsat Vsat21 Sm Min. 335 400 400 -100 Smear -94 -88 Video signal shading Dark signal Dark signal shading Lag SH Vdt Vdt Lag -92 -86 -80 20 25 8 2 0.5 mV mV % 5 6 7 % 4 dB 3 Typ. 420 Max. 545 Unit mV mV Measurement method 1 2
(Ta = 25C) Remarks 1/30s accumulation Ta = 60C No line addition2 2-line addition3
Progressive scan mode4 2/4-line readout mode5 2/8-line readout mode6 Zone 0 and I Zone 0 to II' Ta = 60C, 14.985 frame/s Ta = 60C, 14.985 frame/s, 7
1 Vsat2 is the saturation signal level in 2-line addition mode, and is 200mV per pixel. 2 Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, and center scan modes (1) and (3). 3 2-line addition mode and center scan mode (2). 4 Same for 2-line addition mode and center scan modes (2) and (3). 5 Same for center scan mode (1). 6 Same for AF modes (1) and (2). 7 Excludes vertical dark signal shading caused by vertical register high-speed transfer. - 11 -
ICX274AL
Zone Definition of Video Signal Shading
1628 (H) 4 4 8 H 8 V 10 H 8
1236 (V)
Zone 0, I Zone II, II' V 10
8
Ignored region Effective pixel region
Measurement System
CCD signal output [A]
CCD
C.D.S
AMP
S/H
Signal output [B]
Note) Adjust the AMP gain so that the gain between [A] and [B] equals 1.
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ICX274AL
Readout modes The diagrams below and on the following pages show the output methods for the following nine readout modes. Progressive scan mode 2/8-line readout mode 2/4-line readout mode
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A) VOUT
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A)
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A)
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out. Output starts from line 1 in 2/8-line decimation mode. 1. Progressive scan mode In this mode, all pixel signals are output in non-interlace format in 1/14.985s. All pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. 2. 2/8-line readout mode All effective area signals are output in approximately 1/30s by reading out the signals for only two out of eight lines (1st and 6th lines, 9th and 14th lines). This readout mode emphasizes processing speed over vertical resolution, making it suitable for AE/AF and other control and for checking images on LCD viewfinders. 3. 2/4-line readout mode All effective area signals are output in approximately 1/20s by reading out the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on).
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ICX274AL
2-line addition mode
Center scan mode (1)
Center scan mode (2)
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A)
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A)
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A) VOUT
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out. After reading out the pixels indicated by and transferring two lines, the pixels indicated by are read out and two pixels of the same color are added by the vertical transfer block. 4. 2-line addition mode In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register. All effective area signals are output in approximately 1/20s. 5. Center scan mode (1) In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out. The undesired portions are swept by vertical register high-speed transfer, and the vertical 1136-pixel region in the center of the picture is output by the above readout method. The number of output lines is 568 lines at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased (approximately 30 frames/s) by setting the number of output lines to that of VGA mode, making this mode suitable for VGA moving pictures. (However, the angle of view decreases.) 6. Center scan mode (2) In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register. The undesired portions are swept by vertical register high-speed transfer, and the vertical 1136-pixel region in the center of the picture is output by the above readout method. The number of output lines is 568 lines at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased (approximately 30 frames/s) by setting the number of output lines to that of VGA mode, making this mode suitable for VGA moving pictures. (However, the angle of view decreases.) - 14 -
ICX274AL
Center scan mode (3)
AF mode (1)
AF mode (2)
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A) VOUT
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A) VOUT
16 (V2C/V3C) 15 (V2C/V3C) 14 (V2A/V3A) 13 (V2B/V3B) 12 (V2C/V3C) 11 (V2C/V3C) 10 (V2B/V3B) 9 (V2A/V3A) 8 (V2C/V3C) 7 (V2C/V3C) 6 (V2A/V3A) 5 (V2B/V3B) 4 (V2C/V3C) 3 (V2C/V3C) 2 (V2B/V3B) 1 (V2A/V3A)
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out. 7. Center scan mode (3) This is the center scan mode using the progressive scan method. The undesired portions are swept by vertical register high-speed transfer, and the picture center is cut out. The number of output lines is 580 lines at 36MHz, and 444 lines at 28.6364MHz. 8. AF mode (1) In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical 940-pixel region in the center of the picture is output in approximately 1/60s by reading out the signals for only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 235 lines at 36MHz, and 170 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout mode. 9. AF mode (2) In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical 300-pixel region in the center of the picture is output in approximately 1/120s by reading out the signals for only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 75 lines at 36MHz, and 43 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout mode.
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ICX274AL
Center scan and AF modes
Undesired portions (Swept by vertical register high-speed transfer)
Picture center cut-out portion
Description of Center Scan and AF Mode Operation The center scan and AF modes realize high frame rates by sweeping the top and bottom of the picture with high-speed transfer and cutting out the center of the picture. The various readout modes during center scan and AF operation are described below. * AF modes AF mode (1), (2): The output method is the same as readout in 2/8-line readout mode. * Center scan modes Center scan mode (1): The output method is the same as 2/4-line readout mode. Center scan mode (2): The output method consists of 2-line addition readout whereby the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register. Center scan mode (3): The output method is the same as progressive scan mode. The readout method, frame rate, number of output lines and other information for each readout mode are shown in the table below. Addition method None None None Vertical 2-line None None None None - 16 - Number of output Frame rate (frame/s) effective pixel data lines 28.6MHz Progressive scan mode 2/8-line readout mode 2/4-line readout mode 2-line addition mode Center scan mode (1) Center scan mode (2) Center scan mode (3) AF mode (1) AF mode (2) Progressive scan 2/8-line readout 2/4-line readout 2/4-line readout 2/4-line readout Progressive scan 2/8-line readout 2/8-line readout 9.99 29.97 19.98 19.98 29.97 29.97 29.97 59.94 119.88 36MHz 14.985 29.97 19.98 19.98 29.97 29.97 29.97 59.94 119.88 28.6MHz 1220 305 610 1220 434 434 444 170 43 36MHz 1220 305 610 1220 568 568 580 235 75
Mode
Readout method
2-line addition readout Vertical 2-line
ICX274AL
Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the progressive scan readout mode is used. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value measured at point [*B] of the measurement system. Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to the standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal output (Vs) at the center of the screen, and substitute the values into the following formulas. S = Vs x 100 [mV] 30 2. Saturation signal Set to the standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the G chanel signal output, 150mV, measure the minimum values of the signal outputs. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) of the signal outputs, and substitute the values into the following formula. Smear in modes other than progressive scan mode is calculated from the storage time and signal addition method. As a result, 2-line addition mode and center scan modes (2) and (3) are the same as progressive scan mode, 2/4-line readout mode and center scan mode (1) are two times progressive scan mode, and 2/8-line readout mode and AF modes (1) and (2) are four times progressive scan mode. Sm = 20 x log Vsm x 1 x 1 200 500 10 [dB] (1/10 V method conversion value) - 17 -
ICX274AL
4. Video signal shading Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the signal output is 150mV. Then measure the maximum value (Vmax [mV]) and minimum value (Vmin [mV]) of the G signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/150 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Lag Adjust the signal output generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%]
VD
Light Strobe light timing
Signal output 150mV Output
Vlag (lag)
- 18 -
Drive Circuit
1 2 3 4 5 0.1 0.1 7 8 9 10 11 0.1 -7.5V 1 2 3 4 1
V4 V3A V3B V2A V3C V2B V2C
15V 20 19 18 17 16 CXD3400N 15 14 13 12 100k
3.3V
0.1
XV3
XSG3C 6
XV2
XSG2C
0.1 20 19 18 17 2 3 4 5 6 7 16 CXD3400N 15 14 13
H2A H1A VL
XSUB
1/35V 2SC4250 8
V1
XV3
XSG3B 5 6 7 8 9 10 11 12 0.1 0.1
9 10
GND VOUT
CSUB
SUB
GND
H1B
H2B
RG
XV4
XV1
20 19 18 17 16 15 14 13 12 11
VDD
- 19 -
3.3/16V 0.1 0.1 Substrate bias adjustment input voltage (VSUB in the circuit diagram above) 2200p Substrate bias SUB pin voltage
XSG3A
CCD OUT 4.7k
XV2
XSG2B
ICX274 (BOTTOM VIEW)
3.3/20V 0.01
XSG2A
H1A 1M
VSUB
H2A
H1B
H2B
RG
DCIN GND 2-line addition mode VSUB2 Center scan mode (2) Modes other than the above VSUB (Internally generated value)
Note) Substrate bias control Switch the substrate bias adjustment input voltage to DCIN before adjusting the substrate bias in 2-line addition mode and center scan mode (2).
ICX274AL
Drive Timing Chart (Vertical Sync)
Progressive Scan Mode
VD
HD
1249 1250 1251 1252 1492 1493 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1249 1250 1251 1252
1492 1493 1 2 3 4 5 6 7 8 9 10 11 12 13 14
"a"
"a"
V1
V2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
1235 1236
CCD OUT
36MHz
1235 1236
28.6MHz
36MHz
Note) The 1252H horizontal period at 36MHz is 480clk; the 1493H horizontal period at 28MHz is 1860clk.
28.6MHz
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
- 20 -
ICX274AL
V3
V4
Drive Timing Chart (Horizontal Sync)
Progressive Scan Mode
1920
1
CLK
204 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
- 21 -
18 1 54 1 90 1 1 36 90 54 1 54 1
1
132
V1
1
96
V2A/V2B/V2C
1
V3A/V3B/V3C
114
V4
1
1
78
1 135
60 1 9
SUB
1
296
ICX274AL
Drive Timing Chart (Vertical Sync)
Progressive Scan Mode
"a" enlarged
H1A/H1B
V1
1100 1250
V2A/V2B/V2C
V3A/V3B/V3C
- 22 -
V4
18 18 18 18 18 18 18 18 60
18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Progressive Scan Mode (With Mechanical Shutter)
VD
HD
70 72 1321 1564 1565 1742 1
"b"
1 2 3 4 5 6 7 8 9 10 11
"a"
V1
V2A/V2B/V2C
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
CCD OUT
1235 1236
36MHz
ICX274AL
Note) The 1564 and 1565H horizontal periods at 36MHz are 1021clk; the 1742H horizontal period at 28MHz is 1530clk.
28.6MHz
- 23 -
CLOSE
V3A/V3B/V3C
V4
SUB
TRG
Mechanical shutter
OPEN
Drive Timing Chart (Vertical Sync)
Progressive Scan Mode (With Mechanical Shutter)
"b" enlarged
134400 bits
H1A/H1B
1
18 18 18 18 18 18 18 18 60
V1
V2C
V2A/V2B
- 24 -
#3 #1865
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
ICX274AL
Drive Timing Chart (Vertical Sync)
2/8-line Readout Mode
VD
HD
311 312 406 407 510 511 1 2 3 4 5 6 7 8 9 10 11 12 13 14
311 312
406 407
510 511 1 2 3 4 5 6 7 8 9 10 11 12 13 14
"a"
"a"
V1
V2A
V2B/V2C
1225 1230 1233
3 8 1 6 9 14 17 22 25 30 33 38 41 46
CCD OUT
36MHz
1225 1230 1233
28.6MHz
ICX274AL
Note) The 511H horizontal period at 36MHz is 1680clk; the 406 and 407H horizontal periods at 28MHz are 1470clk.
28.6MHz
36MHz
3 8 1 6 9 14 17 22 25 30 33 38 41 46
- 25 -
V3A
V3B/V3C
V4
Drive Timing Chart (Horizontal Sync)
2/8-line Readout Mode
2352
1
CLK
636 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
1 1 1 1 1 1 90 1 90 1 90 1 54 1 90 1 54 54 1 54 1 1 90 1 54 1 54 90 1 90 1 54 54 1 1 90 1 54 1 54 1 90 1 54 1 90 1 90 54 1 1 54 1 54 1 54 90 1 90 1 90 1 90 1 90
54
1
54
1
54
1
54 1 90 1 90 1 90 1 90 1 90 54 54 1 1 72
1
60
V1
1
18
1
54
36 1
60
V2A
1
54
36 1
60
V2B/V2C
1
V3A
54 1
60
1
V3B/V3C
54 1
60
1
V4
1
36
1 1 18 567 1
60
SUB
1
60 19
728
- 26 -
ICX274AL
Drive Timing Chart (Vertical Sync)
2/8-line Readout Mode
"a" enlarged
H1A/H1B
V1
1100 1250
V2A
V2B/V2C
V3A
- 27 -
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
V3B/V3C
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 42
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 60 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
2/4-line Readout Mode
VD
HD
652 693 871 1 2 3 4 5 6 7 8 9 10
625
693
871 1 2 3 4 5 6 7 8 9 10
"a" "a"
V1
V2C
V2A/V2B
1231 1232 1235 1236
5 6 9 10 3 4 7 8
CCD OUT
36MHz
1231 1232 1235 1236
28.6MHz
28.6MHz
36MHz
5 6 9 10 3 4 7 8
- 28 -
V3C
V3A/V3B
V4
ICX274AL
Note) The 871H horizontal period at 36MHz is 900clk; the 693H horizontal period at 28MHz is 810clk.
Drive Timing Chart (Horizontal Sync)
2/4-line Readout Mode
2070
1
CLK
354 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
- 29 -
18 1 54 1 90 1 1 36 1 90 54 54 1 1 54 1 54 1 90 54 1 54 1 90 1
1
138
V1
1
1 54
102
V2A/V2B/V2C
1
V3A/V3B/V3C
1 90 1
120
V4
1
84
1 282
60 1 12
SUB
1
446
ICX274AL
Drive Timing Chart (Vertical Sync)
2/4-line Readout Mode
"a" enlarged
H1A/H1B
V1
600 750
V2C
V2A/V2B
- 30 -
54 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 54
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
150
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
2-line Addition Mode
VD
HD
625 693 871 1 2 3 4 5 6 7 8 9 10
625
693
871 1 2 3 4 5 6 7 8 9 10
"a"
"a"
V1
V2C
V2A/V2B
5 6 9 10 3 4 7 8
1229 1231 1230 1232 1233 1235 1234 1236 1 2
3 4 7 8 1 2 5 6
36MHz
1229 1230 1233 1234 1 2
28.6MHz
28.6MHz
36MHz
3 4 7 8 1 2 5 6
CCD OUT
1231 1232 1235 1236
5 6 9 10 3 4 7 8
- 31 -
ICX274AL
V3C
V3A/V3B
V4
Note) The 871H horizontal period at 36MHz is 900clk; the 693H horizontal period at 28MHz is 810clk.
Drive Timing Chart (Horizontal Sync)
2-line Addition Mode
2070
1
CLK
354 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
1 1 54 1 90 1 1 36 1 90 54 54 1 1 54 1 54 1 90 54 1 54
18
1
90
1
138
- 32 -
1
V1
1
1 54
102
V2A/V2B/V2C
1
V3A/V3B/V3C
120 90 1 84
V4
1
1 282
60 1 12
SUB
1
446
ICX274AL
Drive Timing Chart (Vertical Sync)
2-line Addition Mode
"a" enlarged
H1A/H1B
V1
600 750
V2C
V2A/V2B
- 33 -
54 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 54
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
150
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1)/(28.6MHz)
VD
HD
15 17 15 450 451 452 453 459 460 461 462 1 2 3 4 5 6 7 8 9 10 17 188 191 192 188 191 192 195
450 451 452 453
"d"
458 459 460 461 462 1 2 3 4 5 6 7 8 9 10
"a" "b"
"d"
"a" "b"
V1
V2C
1052 1055
CCD OUT
ICX274AL
Note) The 462H horizontal period is 1230clk.
1048 1051 1052 1055
- 34 -
V2A/V2B
V3C
V3A/V3B
V4
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1)/(36MHz)
VD
HD
576 577 578 579 580 581 1 2 3 4 5 6 7 8 9 10
576 577 578 579 580 581 1 2 3 4 5 6 7 8 9 10
"d"
"a" "b"
"d"
"a" "b"
V1
V2C
55 56 59 60
CCD OUT
ICX274AL
Note) The 581H horizontal period is 601clk.
1183 1184 1187 1188
1183 1184 1187 1188
55 56 59 60
- 35 -
V2A/V2B
V3C
V3A/V3B
V4
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1)
"a" enlarged
H1A/H1B
V1
600 750
V2C
V2A/V2B
- 36 -
54
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1)/(28.6MHz)
"b" enlarged
28980 bits = 14H 27936 bits
H1A/H1B
V1
V2C
V2A/V2B
- 37 -
#6
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#5
#187
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1)/(36MHz)
"b" enlarged
10350 bits = 5H 8784 bits
H1A/H1B
V1
V2C
V2A/V2B
- 38 -
#6
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#5
#52
ICX274AL
1050 1052 1053 1055
Center Scan Mode (2)/(28.6MHz)
186 189 190 193
188 191 192 195
1046 1049 1050 1053
1048 1051 1052 1055
186 189 190
188 191 192
- 39 -
HD V3A/V3B V2A/V2B V3C V2C VD V4 V1
Drive Timing Chart (Vertical Sync)
CCD OUT
"d" "a" "b"
ICX274AL
Note) The 462H horizontal period is 1230clk.
452 453 454 455 456 457 458 459 460 461 462 1 2 3 4 5 6 7 8 9 10
15 18
"d" "a" "b"
452 453 454 455 456 457 458 459 460 461 462 1 2 3 4 5 6 7 8 9 10
15 18
Drive Timing Chart (Vertical Sync)
Center Scan Mode (2)/(36MHz)
VD
HD
576 577 578 579 580 581 1 2 3 4 5 6 7 8 9 10
576 577 578 579 580 581 1 2 3 4 5 6 7 8 9 10
"d"
"a" "b"
"d"
"a" "b"
V1
V2C
55 56 59 60
1181 1182 1185 1186
53 54 57 58
1181 1182 1185 1186
53 54 57 58
CCD OUT
1183 1184 1187 1188
1183 1184 1187 1188
55 56 59 60
- 40 -
V2A/V2B
V3C
V3A/V3B
V4
ICX274AL
Note) The 581H horizontal period is 601clk.
Drive Timing Chart (Vertical Sync)
Center Scan Mode (2)
"a" enlarged
H1A/H1B
V1
600 750
V2C
V2A/V2B
- 41 -
54 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 66
54
150
18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (2)/(28.6MHz)
"b" enlarged
28980 bits = 14H 27936 bits
H1A/H1B
V1
V2C
V2A/V2B
- 42 -
# (4 + 6)
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
# (3 + 5)
# (185 + 187)
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (2)/(36MHz)
"b" enlarged
10350 bits = 5H 8784 bits
H1A/H1B
V1
V2C
V2A/V2B
- 43 -
# (4 + 6)
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
# (3 + 5)
# (50 + 52)
ICX274AL
Drive Timing Chart (Horizontal Sync)
Center Scan Modes (1) and (2)
2070
1
CLK
354 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
1 1 54 1 90 1 1 36 1 90 54 54 1 1 54 1 90 1 90 54 1 54
18
1
90
1
138
- 44 -
1
V1
1
1 54
102
V2A/V2B/V2C
1
V3A/V3B/V3C
120 90 1 84
V4
1
1 282
60 1 12
SUB
1
446
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Modes (1) and (2)/(28.6MHz)
"d" enlarged
16560 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 45 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#222
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Modes (1) and (2)/(36MHz)
"d" enlarged
6210 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 46 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#63
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(28.6MHz)
VD
HD
32 33 34 35 478 479 496 497 498 1 2 3 4 5 6 32 33 34 35 397 398
478 479
"d"
496 497 498 1 2 3 4 5 6
"a"
"b"
"d"
"a" "b"
V1
V2
839 840
CCD OUT
397 398
Note) The 498H horizontal period is 1260clk.
839 840
- 47 -
V3
V4
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(36MHz)
VD
HD
27 28 29 30 31 609 610 624 625 626 1 2 3 4 5 6 27 28 29 30 329 330
609 610
"d"
624 625 626 1 2 3 4 5 6
"a"
"b"
"d"
"a" "b"
V1
V2
907 908
CCD OUT
329 330
Note) The 626H horizontal period is 1200clk.
907 908
- 48 -
V3
V4
ICX274AL
Drive Timing Chart (Horizontal Sync)
Center Scan Mode (3)
1920
1
CLK
204 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
- 49 -
18 1 54 1 90 1 1 36 90 54 1 54 1
1
132
V1
1
96
V2A/V2B/V2C
1
V3A/V3B/V3C
114
V4
1
1
78
1 135
60 1 9
SUB
1
296
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)
"a" enlarged
H1A/H1B
V1
1100 1250
V2A/V2B/V2C
V3A/V3B/V3C
- 50 -
18 18 18 18 18
V4
18 18 18 18 18 18 18 18 60
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(28.6MHz)
"b" enlarged
59520 bits = 31H 58608 bits
H1A/H1B
V1
V2C
V2A/V2B
- 51 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(36MHz)
"b" enlarged
49920 bits = 26H 48816 bits
H1A/H1B
V1
V2C
V2A/V2B
- 52 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(28.6MHz)
"d" enlarged
34560 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 53 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#398
ICX274AL
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)/(36MHz)
"d" enlarged
28800 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 54 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#330
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(28.6MHz)
VD
HD
19 20 21 22 190 191 201 202 203 204 1 2 3 4 5 6 7 8 9 19 20 21 22 286 289 953 958
190 191
"d"
201 202 203 204 1 2 3 4 5 6 7 8
"a"
"b"
"d"
"a" "b"
V1
V2A
953 958
CCD OUT
286 289
- 55 -
V2B/V2C
V3A
V3B/V3C
V4
ICX274AL
Note) The 203 and 204H horizontal periods are 1323clk.
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(36MHz)
VD
HD
248 249 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14
248 249
"d"
254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14
"a"
"b"
"d"
"a" "b"
V1
V2A
1086 1089
153 158
CCD OUT
ICX274AL
Note) The 256H horizontal period is 840clk.
1086 1089
153 158
- 56 -
V2B/V2C
V3A
V3B/V3C
V4
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(28.6MHz)
"b" enlarged
42336 bits = 18H 41904 bits
H1A/H1B
V1
V2C
V2A/V2B
- 57 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(36MHz)
"b" enlarged
23520 bits = 10H 22896 bits
H1A/H1B
V1
V2C
V2A/V2B
- 58 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(28.6MHz)
"d" enlarged
25872 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 59 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#339
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (1)/(36MHz)
"d" enlarged
14112 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 60 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#180
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(28.6MHz)
VD
HD
35 36 37 38 80 81 100 101 102 1 2 3 4 5 6 7 8 9 35 36 37 38 537 542 702 705
80 81
"d"
100 101 102 1 2 3 4 5 6 7 8 9
"a"
"b"
"d"
"a" "b"
V1
V2A
702 705
CCD OUT
537 542
- 61 -
V2B/V2C
V3A
V3B/V3C
V4
ICX274AL
Note) The 102H horizontal period is 1323clk.
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(36MHz)
VD
HD
31 32 33 34 108 109 126 127 128 1 2 3 4 5 6 7 8 9 31 32 33 34 473 478 766 769
108 109
"d"
126 127 128 1 2 3 4 5 6 7 8 9
"a" "b"
"d"
"a" "b"
V1
V2A
766 769
CCD OUT
473 478
- 62 -
V2B/V2C
V3A
V3B/V3C
V4
ICX274AL
Note) The 128H horizontal period is 1596clk.
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(28.6MHz)
"b" enlarged
79968 bits = 34H 78192 bits
H1A/H1B
V1
V2C
V2A/V2B
- 63 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(36MHz)
"b" enlarged
70560 bits = 30H 68976 bits
H1A/H1B
V1
V2C
V2A/V2B
- 64 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(28.6MHz)
"d" enlarged
47040 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 65 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#640
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Mode (2)/(36MHz)
"d" enlarged
42336 bits
H1A/H1B
1
V1
V2C
V2A/V2B
- 66 -
V3C
V3A/V3B
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
#1
#2
#3
#564
ICX274AL
Drive Timing Chart (Horizontal Sync)
AF Modes (1) and (2)
2352
1
CLK
636 1 28 1 12
1
52 1
H1A/H1B
14
H2A/H2B
RG
SHP
SHD
- 67 -
54 1 1 1 1 1 90 1 90 1 90 1 54 1 1 90 54 54 1 54 1 1 90 1 54 1 54 90 1 90 1 54 54 1 1 90 1 90 1 54 1 54 1 54 1 54 1 90 1 90 1 54 1 54 1 54 90 1 90 1 90 1 90 1 90 1 90 90 1 1 54 1 54 1 54 1
1
1 72 1 54 1 54 90 1 90 1 90 1 1 18 567 1 54 1 54 1 36 1 36 1
60
V1
1
18
1
54
60
V2A
1
54
60
V2B/V2C
1
V3A
60
1
V3B/V3C
60
1
V4
1
36
60
SUB
1
60 19
728
ICX274AL
Drive Timing Chart (Vertical Sync)
AF Modes (1) and (2)
"a" enlarged
H1A/H1B
V1
1100 1250
V2A
V2B/V2C
V3A
- 68 -
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
V3B/V3C
V4
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 42
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 60 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
ICX274AL
ICX274AL
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.)
Cover glass
50N Plastic package Compressive strength
50N
1.2Nm Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 69 -
ICX274AL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same.
Structure A Package Chip Metal plate (lead frame)
Structure B
Cross section of lead frame
The cross section of lead frame can be seen on the side of the package for structure A.
- 70 -
Package Outline
Unit: mm
20 pin DIP
0 to 9
6.9
D
A
2.5
20 11 11
1.7
20 1.7
~
C
2.5
10.9
12.2
B
9.0
1.7
1.7
~
6.0
H 0.25 1
0.5
0.8 13.8 0.1
B' 0.5 0.8 2.9 0.15
12.7
10 10
1
10.0
2.5
12.0 0.1
V
1.27 0.3
3.5 0.3
2.4
- 71 -
1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (6.9, 6.0) 0.075mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.49 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 50m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 50m. 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing.
ICX274AL
~
0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Plastic
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.95g
Sony Corporation
DRAWING NUMBER
AS-B6-04(E)

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